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- Ellervee, Peeter, et al.
(författare)
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Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
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Ingår i: Proc. of IEEE ASIC-conference, 1994.
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Konferensbidrag (refereegranskat)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
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| 7. |
- Hemani, Ahmed, et al.
(författare)
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High-level synthesis of control and memory intensive communication systems
- 1995
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Ingår i: ; , s. 185-191
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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| 9. |
- Jantsch, Axel, et al.
(författare)
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A Case Study on Hardware/Software Partitioning
- 1994
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Ingår i: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines. - : IEEE conference proceedings. - 0818654902 ; , s. 111-118
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Konferensbidrag (refereegranskat)abstract
- We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.
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